From 1c233d5be8b0a1c6cdf5aa1ec3e888d636dea36e Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Thu, 1 Aug 2019 23:35:33 +0300 Subject: [PATCH 09/23] clk: renesas: r8a77970-cpg-mssr: Fix SD clock This fixes SD0 clock parent, and uses custom divisor ratio table and mask value because V3M SD-IF0 register settings differ from other R-Car Gen3 variants. Signed-off-by: Valentine Barshak --- drivers/clk/renesas/r8a77970-cpg-mssr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 961eb7f..3151761 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -84,7 +84,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = { DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1), - DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074), + DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV2, 0x0074), DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238), @@ -193,6 +193,11 @@ static const struct mstp_stop_table r8a77970_mstp_table[] = { { 0x000000B7, 0x0, 0x000000B7, 0 }, }; +static const struct cpg_sd_div_table r8a77970_sd_div_table[] = { + { 4 << 4, 8 }, { 5 << 4, 12 }, { 6 << 4, 16 }, { 7 << 4, 18 }, + { 8 << 4, 24 }, { 10 << 4, 36 }, { 11 << 4, 48 }, { 12 << 4, 10 }, +}; + static const void *r8a77970_get_pll_config(const u32 cpg_mode) { return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; @@ -205,6 +210,9 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks), .mstp_table = r8a77970_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), + .sd_div_table = r8a77970_sd_div_table, + .sd_div_table_size = ARRAY_SIZE(r8a77970_sd_div_table), + .sd_div_mask = 0xff << 4, .reset_node = "renesas,r8a77970-rst", .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, -- 2.7.4