Data Fields
CSL_DssVpLcdBlankTimingCfg Struct Reference

Blanking Timing parameters for the LCD. More...

#include <csl_dssVideoPort.h>

Data Fields

uint32_t hFrontPorch
 
uint32_t hBackPorch
 
uint32_t hSyncLen
 
uint32_t vFrontPorch
 
uint32_t vBackPorch
 
uint32_t vSyncLen
 

Detailed Description

Blanking Timing parameters for the LCD.

Field Documentation

uint32_t CSL_DssVpLcdBlankTimingCfg::hBackPorch

Horizontal Back Porch, specifies the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field. In case of BT progressive mode this field is unused

uint32_t CSL_DssVpLcdBlankTimingCfg::hFrontPorch

Horizontal Front Porch, specifies the number of pixel clock periods to add to the end of a line transmission before line clock is asserted. In BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field. In case of BT progressive mode this field is unused

uint32_t CSL_DssVpLcdBlankTimingCfg::hSyncLen

Horizontal synchronization pulse width, Encoded Value(from 1 to 256)to specify the number of pixel clock periods to pulse the line clock at the end of each line. In BT mode, this field corresponds to 12-bit horizontal blanking

uint32_t CSL_DssVpLcdBlankTimingCfg::vBackPorch

Vertical back porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display

uint32_t CSL_DssVpLcdBlankTimingCfg::vFrontPorch

Vertical front porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2

uint32_t CSL_DssVpLcdBlankTimingCfg::vSyncLen

Vertical synchronization pulse width In active mode, RW 0x00 encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In BT mode, this field is not used


The documentation for this struct was generated from the following file:

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